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rej03c0109-0201 rev.2.01 page 1 of 11 jun 16, 2010 datasheet r1rw0416di series wide temperature range version 4m high speed sram (256-kword 16-bit) description the r1rw0416di is a 4-mbit high speed static ram or ganized 256-kword 16-bit. it has realized high speed access time by employing cmos process (6-transistor memory cell) and high speed circuit designing technology. it is most appropriate for the application which requires high speed, high density memory and wide bit width conf iguration, such as cache and buffer memory in system. the r1rw0416 di is packaged in 400-mil 44-pin soj and 400-mil 44 -pin plastic tsopii for high density surface mounting. features ? single 3.3 v supply: 3.3 v 0.3 v ? access time: 10ns/12 ns (max) ? completely static memory ? no clock or timing strobe required ? equal access and cycle times ? directly ttl compatible ? all inputs and outputs ? operating current: 145/130 ma (max) ? ttl standby current: 40 ma (max) ? cmos standby current: 5 ma (max) ? center v cc and v ss type pin out ? temperature range: ? 40 to +85 c ordering information type no. access time package R1RW0416DGE-0PI 10ns r1rw0416dge-2pi 12 ns 400-mil 44-pin plastic soj (44p0k) r1rw0416dsb-0pi 10 ns r1rw0416dsb-2pi 12 ns 400-mil 44-pin plastic tsopii (44p3w-h) rej03c0109-0201 rev.2.01 jun 16, 2010
r1rw0416di series rej03c0109-0201 rev.2.01 page 2 of 11 jun 16, 2010 pin arrangement pin description pin name function a0 to a17 address input i/o1 to i/o16 data input/output cs# chip select oe# output enable we# write enable ub# upper byte select lb# lower byte select v cc power supply v ss ground nc no connection
r1rw0416di series rej03c0109-0201 rev.2.01 page 3 of 11 jun 16, 2010 block diagram
r1rw0416di series rej03c0109-0201 rev.2.01 page 4 of 11 jun 16, 2010 operation table cs# oe# we# lb# ub# mode v cc current i/o1 ? ?? ? i/o8 i/o9 ? ?? ? i/o16 ref. cycle h standby i sb , i sb1 high-z high-z ? l h h output disable i cc high-z high-z ? l l h l l read i cc output output read cycle l l h l h lower byte read i cc output high-z read cycle l l h h l upper byte read i cc high-z output read cycle l l h h h ? i cc high-z high-z ? l l l l write i cc input input write cycle l l l h lower byte write i cc input high-z write cycle l l h l upper byte write i cc high-z input write cycle l l h h ? i cc high-z high-z ? note: h: v ih , l: v il , : v ih or v il absolute maximum ratings parameter symbol value unit supply voltage relative to v ss v cc ? 0.5 to +4.6 v voltage on any pin relative to v ss v t ? 0.5 * 1 to v cc + 0.5 * 2 v power dissipation p t 1.0 w operating temperature topr ? 40 to +85 c storage temperature tstg ? 55 to +125 c storage temperature under bias tbias ? 40 to +85 c notes: 1. v t (min) = ? 2.0 v for pulse width (under shoot) 6 ns 2. v t (max) = v cc + 2.0 v for pulse width (over shoot) 6 ns
r1rw0416di series rej03c0109-0201 rev.2.01 page 5 of 11 jun 16, 2010 recommended dc operating conditions (ta = ? 40 to +85 c) parameter symbol min typ max unit supply voltage v cc * 3 3.0 3.3 3.6 v v ss * 4 0 0 0 v input voltage v ih 2.0 ? v cc + 0.5 * 2 v v il ? 0.5 * 1 ? 0.8 v notes: 1. v il (min) = ? 2.0 v for pulse width (under shoot) 6 ns 2. v ih (max) = v cc + 2.0 v for pulse width (over shoot) 6 ns 3. the supply voltage with all v cc pins must be on the same level. 4. the supply voltage with all v ss pins must be on the same level. dc characteristics (ta = ? 40 to +85 c, v cc = 3.3 v 0.3 v, v ss = 0 v) parameter symbol min max unit test conditions input leakage current |i li | ? 2 a v in = v ss to v cc output leakage current |i lo | ? 2 a v in = v ss to v cc operating power supply current i cc ? 130 ma min cycle cs# = v il , i out = 0 ma other inputs = v ih /v il standby power supply current i sb ? 40 ma min cycle, cs# = v ih , other inputs = v ih /v il i sb1 ? 5 ma f = 0 mhz v cc cs# v cc ? 0.2 v, (1) 0 v v in 0.2 v or (2) v cc v in v cc ? 0.2 v output voltage v ol ? 0.4 v i ol = 8 ma v oh 2.4 ? v i oh = ? 4 ma capacitance (ta = +25 c, f = 1.0 mhz) parameter symbol min max unit test conditions input capacitance * 1 c in ? 6 pf v in = 0 v input/output capacitance * 1 c i/o ? 8 pf v i/o = 0 v note: 1. this parameter is sampled and not 100% tes ted.
r1rw0416di series rej03c0109-0201 rev.2.01 page 6 of 11 jun 16, 2010 ac characteristics (ta = ? 40 to +85 c, v cc = 3.3 v 0.3 v, unless otherwise noted.) test conditions ? input pulse levels: 3.0 v/0.0 v ? input rise and fall time: 3 ns ? input and output timing reference levels: 1.5 v ? output load: see figures (including scope and jig) read cycle r1rw0416di 10ns version 12ns version parameter symbol min max min max unit notes read cycle time t rc 10 ? 12 ? ns address access time t aa ? 10 ? 12 ns chip select access time t acs ? 10 ? 12 ns output enable to output valid t oe ? 5 ? 6 ns byte select to output valid t ba ? 5 ? 6 ns output hold from address change t oh 3 ? 3 ? ns chip select to output in low-z t clz 3 ? 3 ? ns 1 output enable to output in low-z t olz 0 ? 0 ? ns 1 byte select to output in low-z t blz 0 ? 0 ? ns 1 chip deselect to output in high-z t chz ? 5 ? 6 ns 1 output disable to output in high-z t ohz ? 5 ? 6 ns 1 byte deselect to output in high-z t bhz ? 5 ? 6 ns 1
r1rw0416di series rej03c0109-0201 rev.2.01 page 7 of 11 jun 16, 2010 write cycle r1rw0416di 10ns version 12ns version parameter symbol min max min max unit notes write cycle time t wc 10 ? 12 ? ns address valid to end of write t aw 7 ? 8 ? ns chip select to end of write t cw 7 ? 8 ? ns 8 write pulse width t wp 7 ? 8 ? ns 7 byte select to end of write t bw 7 ? 8 ? ns address setup time t as 0 ? 0 ? ns 5 write recovery time t wr 0 ? 0 ? ns 6 data to write time overlap t dw 5 ? 6 ? ns data hold from write time t dh 0 ? 0 ? ns write disable to output in low-z t ow 3 ? 3 ? ns 1 output disable to output in high-z t ohz ? 5 ? 6 ns 1 write enable to output in high-z t whz ? 5 ? 6 ns 1 notes: 1. transition is measured 200 mv from steady voltage with output load (b). thi s parameter is sampled and not 100% tested. 2. if the cs# or lb# or ub# low transition occurs si multaneously with the we# low transition or after t he we# transition, output remains a high impedance state. 3. we# and/or cs# must be high during address trans ition time. 4. if cs#, oe#, lb# and ub# are low during this perio d, i/o pins are in the output state. then the data input signals of opposite phase to the outputs must not b e applied to them. 5. t as is measured from the latest address transition to the latest of cs#, we#, lb# or ub# going low. 6. t wr is measured from the earliest of cs#, we#, lb# or ub# going high to the first address transition. 7. a write occurs during the overlap of a low cs#, a low we# and a low lb# or a low ub# (t wp ). a write begins at the latest transition among cs# going low, we# goi ng low and lb# going low or ub# going low. a write ends at the earliest transition among cs# going high , we# going high and lb# going high or ub# going high . 8. t cw is measured from the later of cs# going low to the end of write.
r1rw0416di series rej03c0109-0201 rev.2.01 page 8 of 11 jun 16, 2010 timing waveforms read timing waveform (1) (we# = v ih ) read timing waveform (2) (we# = v ih , lb# = v il , ub# = v il )
r1rw0416di series rej03c0109-0201 rev.2.01 page 9 of 11 jun 16, 2010 write timing waveform (1) (we# controlled)
r1rw0416di series rej03c0109-0201 rev.2.01 page 10 of 11 jun 16, 2010 write timing waveform (2) (cs# controlled)
r1rw0416di series rej03c0109-0201 rev.2.01 page 11 of 11 jun 16, 2010 write timing waveform (3) (lb#, ub# controlled, oe# = v ih )
all trademarks and registered trademarks are the pro perty of their respective owners. c - 1 revision history r1rw0416di series data sheet description rev. date page summary 0.01 sep. 30, 2003 ? initial issue 1.00 mar. 12, 2004 ? - deletion of preliminary 2.00 may. 01, 2009 ? p1 p5 p6/p7 addition of access grade 10ns version. the product lineup :r1rw0416dsb-0pi/dge-0pi is added . operating power supply current of 10ns cycle versio n is described to the dc characteristic. the timing standard of 10ns version is described at the read cycle the timing standard of 10ns version is described at the write cycle 2.01 jun. 16, 2010 ? change the format, ?renesas electronics corporatio n?, all documents should contain the following section break and paragraph as the last item. the footers o f this document refer to the paragraph in order to reference the la st page of the document.
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